1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit which comprises a memory cell array having arranged a plurality of memory cells.
2. Description of the Related Art
Elements that constitute a semiconductor integrated circuit have become finer with the development of semiconductor manufacturing technologies. Finer elements allow semiconductor integrated circuits to reach higher integration at an equal chip size or to reduce the chip size at an equal integration level. For example, in the case of semiconductor memories, finer elements have helped to develop products of greater memory capacity, or of reduced chip size with an equal memory capacity.
Recently, there has been a growing demand for higher performance as well as larger capacity in semiconductor memories such as a dynamic random access memory (DRAM). On this account, for example, when elements are made finer for reduction of chip size, it accompanies speeding up of the operation of predetermined circuits and improvements in access time.
In designing a high-speed circuit, an increase is needed in the amount of electric current to be supplied to the circuit. In order to reduce voltage drops and keep the current density within specifications, the increase in the amount of current in turn requires that power supply lines connected to the circuit be greater in width to reduce their wiring resistances. Due to the finer structure of the elements, however, simply expanding the power supply lines in width increases the layout size of the circuit in proportion to the dimensions of the lines. In other words, the width expansion creates wasted spaces having no elements arranged thereon, lowering the efficiency of the chip size reduction.
In a conventional contrivance to solve such a problem, the power supply lines are formed in a netlike configuration on the unused areas of wiring layers, to lower the wiring resistance and secure a predetermined amount of current.
Additionally, the amount of current supplied to the circuit can also be increased by raising the supply voltage to the circuit. The necessity of the circuit corresponding to a dedicated supply voltage, however, entails a plurality of power supply lines in different voltages within the chip, making each of the power supply lines smaller in wiring width. This may increase a drop in voltage, or cause a current density out of specifications.
FIG. 1 shows a part of a memory core unit of a DRAM which has power supply lines in a netlike configuration.
The semiconductor fabrication process for the DRAM provides wiring layers consisting of, in order from the side closer to the semiconductor substrate, a first polycide-wiring layer, a second polycide-wiring layer, a first metal wiring layer (the dot-dash lines in FIG. 1), and a second metal wiring layer (the broken lines in FIG. 1).
The memory core unit 1 has arranged a rectangular memory cell array 2. The memory cell array 2 comprises a plurality of memory cells MC arranged vertically and horizontally. Sense amplifier rows 3 each having a plurality of sense amplifiers and sub-word decoder rows 4 each having a plurality of sub-word decoders are arranged around the memory cell array 2 along the horizontal direction and the vertical directions, respectively.
In the memory cell array 2 and the sub-word decoder rows 4, a plurality of main-word lines MWL are formed along the horizontal direction using the first metal wiring layer. In each of the sense amplifier rows 3, an internal power supply line VII and a ground line VSS are formed along the horizontal direction using the first metal wiring layer. The internal power supply lines VII and the ground lines VSS are a kind of power supply line. In the sub-word decoder rows 4 and the memory cell array 2, internal power supply lines VII and ground lines VSS are formed along the vertical direction using the second metal wiring layer. The internal power supply lines VII formed of the first metal wiring layer are connected via through holes TH located outside the memory cell array 2 to the internal power supply lines VII formed of the second metal wiring layer. Similarly, the ground lines VSS formed of the first metal wiring layer are connected via through holes TH located outside the memory cell array 2 to the ground lines VSS formed of the second metal wiring layer. In this way, the internal power supply lines VII and the ground lines VSS are formed in a netlike configuration.
This DRAM has word lines of hierarchical structure, consisting of main-word lines MWL and sub-word lines SWL. The sub-word lines SWL are formed along the main-word lines MWL by using the first polycide-wiring layer, on the basis of four to each of the main-word line MWL. The sub-word lines SWL are wired from the sub-word decoder rows 4 to the memory cell array 2. The memory cell array 2 is also provided with a plurality of bit lines BL, which are formed at right angles to the main-word lines MWL by using the second polycide-wiring layer.
Incidentally, in a conventional 4-megabit DRAM or the like, all word lines used to be formed in parallel in a vertical configuration using both the first polycide-wiring layer and the first metal wiring layer. With increasing fineness of the elements, however, it has become difficult to form the word lines of the first metal wiring layer with the same spacing as that between the word lines of the first polycide-wiring layer. Specifically, it has become difficult to ensure wiring spacing which satisfies electromigration specifications. For this reason, the word lines have come to be hierarchically divided into the main-word lines MWL and the sub-word lines SWL as described above, so that only the sub-word lines SWL formed of the first polycide-wiring layer are formed on the memory cells.
Meantime, for further reduction in chip size, it has recently been practiced to reduce the number of sense amplifiers and connect more memory cells MC to each bit line BL, so as to reduce the size of the sense amplifier rows 3. Similarly, it has been practiced to reduce the number of sub-word decoders and connect more memory cells MC to each sub-word line SWL, so as to reduce the size of the sub-word decoder rows 4. The sub-word decoders and the sense amplifiers are circuits which are arranged on the chip with the number second largest to the memory cells MC. Accordingly, the reduction in the number of these circuits has a great effect on the reduction in chip size.
Reducing the sense amplifier rows 3 and the sub-word decoder rows 4 in size, however, tends to decrease the wiring widths of the power supply lines including the internal power supply lines VII and the ground lines VSS arranged over the memory core unit 1. This gives rise to a problem in that the internal power supply lines VII and the ground lines VSS in the netlike configuration shown in FIG. 1 cannot secure the required amount of current.
The amount of electric current on power supply lines can be secured by increasing the thickness of the metal wiring layers to lower the sheet resistance. Thicker metal wiring layers would, however, create higher steps in the chip's sectional direction, contributing to a decrease in yield.
A predetermined amount of current can also be secured by changing the structure of the metal wiring layers from being two-layered to three-layered. The structural change in the metal wiring layers, from being two-layered to three-layered, however, increases the number of processes in fabrication, raises the fabrication cost, and at the same time decreases yield.